Infineon XC2000, XE166 Microcontrollers

UDE Debug, Trace and Test solution for Infineon XC2000, XE166

The Infineon XC2000, XE166 SV2 microcontrollers are the latest derivatives of the popular C166 microcontroller family. Based on the enhanced XC166 architecture they outperform existing 16-bit solutions with 32-bit Performance. Operating at 80 MHz and one cycle per instruction, XC2000, XE166 delivers 80 MIPS, twice the performance compared with its predecessor XC166 and four times the performance of the fastest classic C166 MCU.
In addition, XE166 offers three times more Flash than XC166 with a maximum Flash capacity of 768 kBytes.

Summary of Basic Features of XE166 for Industrial

The high flexibility of this architecture allows to serve the diverse and varying needs of different application areas such as automotive, industrial control, or data communications.

12.5 ns Instruction Cycle Time at 80 MHz CPU Clock (Single-Cycle Execution)
1-cycle Multiplication (16 x 16-bit), Background Division (32-/16-bit) in 21 Cycles
1-cycle Multiply-and-Accumulate (MAC) Instructions
Enhanced Boolean Bit Manipulation Facilities
Zero-Cycle Jump Execution
Additional Instructions to Support HLL and Operating Systems
Register-Based Design with Multiple Variable Register Banks
Fast Context Switching Support with Two Additional Local Register Banks
16 MBytes Total Linear Address Space for Code and Data
1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
Clock Generation via on-chip PLL, or via Prescaler

Bit, byte, and word data types
Flexible and efficient addressing modes for high code density
Enhanced boolean bit manipulation with direct addressability of 6 kbits
for peripheral control and user defined flags
Hardware traps to identify exception conditions during runtime
HLL support for semaphore operations and efficient data access

1 kBytes On-Chip Stand-by RAM (SBRAM)
2 kBytes On-Chip Dual-Port RAM (DPRAM)
16 kBytes On-Chip Data SRAM (DSRAM)
up to 64 kBytes On-Chip Program/Data SRAM (PSRAM)
up to 768 kBytes On-Chip Program Memory (Flash Memory)

Single Power Supply from 3.0 Volts to 5.5 Volts
Multiplexed or demultiplexed bus configurations
Segmentation capability and chip select signal generation
8-bit or 16-bit data bus
Bus cycle characteristics selectable for five programmable address areas
Up to 16 MBytes External Address Space for Code and Data
Hold- and Hold-Acknowledge Bus Arbitration Support

87 Sources with separate interrupt vectors
Sample-Rate down to 12.5 ns
Fast external interrupts

Interrupt driven single cycle data transfer
24-bit Pointers Cover Total Address Space
Eliminates overhead of saving and restoring system state for interrupt requests

Up to 118 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
Two Synchronizable 24-channel A/D Converter with Programmable Resolution (10-bit or 8-bit) and Conversion Time (down to 1.2 µs)
Four 16-channel General Purpose Capture/Compare Units (32 Input/Output Pins)
Multi-Functional General Purpose Timer Unit with 5 Timers
Two Asynchronous/Synchronous Serial Channels (USART) with baud rate generator, parity, framing, and overrun error detection
High Speed Synchronous Serial Channel programmable data length and shift direction
On-Chip MultiCAN Interface (Rev. 2.0B active) with 128 Message Objects (Full CAN/Basic CAN) on Five CAN Nodes and Gateway Functionality
Six serial interface channels to be used as UART, LIN, buffered SPI, IIC Bus Interface, IIS Interface
IIC Bus Interface (10-bit addressing, 400 kbps) with 3 Channels (multiplexed)
On-chip Real Time Clock, Driven by Dedicated Oscillator
ASC Bootstrap loader for flexible system initialization
On-chip Debug Support via JTAG Interface
Enhanced power saving modes with flexible power management