UDE Debug, Trace and Test solution solution for SiFive RISC-V Based Microcontrollers
UDE Debug, Trace and Test solution solution for SiFive RISC-V Microcontrollers and SoCs
RISC-V is an instruction set architecture (ISA) based on the reduced instruction set computer (RISC) design principle. Unlike other architectures, RISC-V is a free and open ISA thanks to the Berkeley Software Distribution (BSD) licensing and it is designed for a wide range of application domains.
Several semiconductor manufacturers have implemented RISC-V-based SoCs (system on a chip) as well as microcontrollers that balance computing power and power consumption.
UDE RISC-V Debug Features
- Support for 32-bit RISC-V ISA
- Support for vendor specific ISA extensions
- Supported calling conventions
- Standard calling convention
- Processor specific Application Binary Interface (psABI) with symbolic names.
- Trace support is in preparation
SiFive RISC-V Microcontrollers and SoCs supported by UDE
- RISC-V E2 series: E20 E21 E24
- RISC-V E31 Core: FE310
- RISC-V E3 series: E31 E34
- RISC-V E7 series: E76
SiFive RISC-V Debug, Trace and Test Features supported by UDE
- Microcontroller debug support
- Multi-core Debugging support
- FLASH Memory programming
- Test Automation and Test Scripting Support with Python and other scripting languages
- FreeRTOS support
- Eclipse Plug-in
UDE - Universal Debug Engine with multi-core support - Cortex Debugger and Emulator for RISC-V
UDE - Universal Debug Engine - is a flexible debug and emulator platform with Multicore debugging for RISC-V.
